1. Field of the Invention
The present invention relates to a NAND flash memory device and a method of fabricating the same, and more particularly, to a NAND flash memory device having a facing bar and a method of fabricating the device.
2. Discussion of Related Art
As shown in FIG. 1, a NAND flash memory device, which is one type of non-volatile memory device, includes a string array STARR in which a plurality of cell strings STG<1:m> are arranged. Each of the cell strings STG<1:m> includes a drain select transistor DST, a plurality of cell transistors MC<1:n>, and a source select transistor SST, which are connected in series between a corresponding one of bit lines BL<1:m> and a common source line CSL. In this case, a drain select signal XDS, word line selection signals WL<1:n>, and a source select signal XSS are applied to the drain select transistor DST, a corresponding one of the plurality of cell transistors MC<1:n>, and the source select transistor SST, respectively, to form transmission channels. Further, to improve characteristics of the NAND flash memory device, a dummy transistor (not shown) having a shape similar to that of the cell transistor MC may be located at an appropriate position of the cell string STG
In this case, each of the cell transistors MC<1:n> is a transistor having a control gate CGT to which a signal for forming the transmission channel is applied and a trap gate TGT configured to trap charges of the transmission channel. In the present specification, the cell transistors MC<1:n> may be called a ‘trap transistor’. Further, the drain select transistor DST and the source select transistor SST form the transmission channel having a control gate CGT to which a signal for forming the transmission channel is applied. The drain select transistor DST and the source select transistor SST are transistors devoid of trap gates and may be referred to as ‘transmission transistors’ in the present specification.
Meanwhile, NAND flash memory devices have lately become gradually highly integrated. In this case, in a conventional NAND flash memory device having a transmission channel formed on a planar surface, a channel length of a cell transistor MC is reduced. Thus, phenomena, such as a short channel effect, a leakage current of a silicon substrate, gate induced drain leakage (GIDL), drain induced barrier lowering (DIBL), program disturbances, and a rise in trap charge loss ratio, occur in the conventional NAND flash memory device. Problems, such as a variation in threshold voltage due to interference between adjacent cell transistors, occur.